The present invention relates to an overlay vernier of a semiconductor device and, more particularly, to an overlay vernier and a method of manufacturing, in which errors in measured values due to the step can be decreased.
In general, a semiconductor manufacturing process includes implementing specific circuits on a wafer by using multiple layers including an insulating layer and a conductive layer. The most fundamental thing is to form specific patterns on the wafer. In particular, in the photo process using a light source and pattern, such as a mask or reticle, reliable semiconductor circuits can be implemented only when an alignment can be performed between a pattern formed in a pre-process and a pattern formed in a post process.
Generally, in the photo process, in order to confirm the degree of alignment between the pre- and post process patterns, a vernier is used. The vernier is formed around a chip of a semiconductor wafer, and is formed within scribe lines, which are cut and removed after the wafer process is completed.
The semiconductor manufacturing process includes multiple steps of pattern formation processes, and therefore employs a reticle in which a specific pattern is formed in each step. A vernier is formed in the reticle used in each step, a vernier formed in the pre-process becomes a reference key, and a vernier formed in the post process becomes a measurement key. Thus, the degree of overlay between the patterns is measured by checking the relative positional relationship between the vernier of the pre-process and the vernier of the post process.
The overlay vernier includes a box-in-box type vernier, a bar-in-bar type vernier, a modified bar-in-bar type vernier and so forth.
The overlay vernier comprises a mother vernier formed in the pre-process and a child vernier formed in a current process. In general, the mother vernier consists of a pattern having the same material as that of an actual cell pattern, and the child vernier consists of a photoresist pattern.
FIGS. 1 to 3 are cross-sectional views illustrating a conventional method of forming an overlay vernier.
Referring to FIG. 1, trenches are formed in the scribe regions of a semiconductor substrate 10 by means of an etch process, so that portions 11 projected from the peri region of the semiconductor substrate 10 are formed. The projected portions 11 are utilized as mother verniers. For reference, the mother verniers include patterns in rectangular form from a plan view.
Referring to FIG. 2, an insulating layer 12 is formed on the entire surface including the mother verniers 11. A polishing process is then performed to expose the top surface of the mother verniers 11.
Referring to FIG. 3, the insulating layer formed in the scribe region is removed by means of an etch process employing a key open mask. Exposure and development processes are then performed on the inner sides of the mother vernier 11 to form a child vernier 13.
However, at the time of the exposure and formation processes, the exposure process is not correctly performed due to the step of the mother vernier 11 and, therefore, the child vernier 13 does not have a square pattern of an accurate box-in-box type or a rectangular pattern of an accurate bar-in-bar type. Accordingly, fail may be caused at the time of a subsequent alignment measurement process, or misalignment may occur upon alignment of a subsequent process due to erroneous data although measurement is successful.